Structure of circuit board and method for fabricating same

ABSTRACT

An embedded semiconductor chip structure and a method for fabricating the same are proposed. The structure comprises: a carrier board, therewith a plurality of through openings formed in the carrier board, and through trenches surrounding the through openings in the same; a plurality of semiconductor chips received in the through openings of the carrier board. Subsequently, cutting is processed via the through trenches. Thus, the space usage of the circuit board and the layout design are more efficient. Moreover, shaping time is also shortened.

FIELD OF THE INVENTION

The present invention relates to a structure with semiconductor chipsembedded therein and a method of fabricating the same, and moreparticularly, to a structure with the semiconductor chip embedded andthe circuit layer integrated therein, and a method of formation thereof.

BACKGROUND OF THE INVENTION

Due to the rapid growth in the electronic industry, electronic deviceshave gradually been developed towards the directions of multi-function,high speed, and high frequency. In the demand of high integration andminiaturization, semiconductor packages have evolved gradually from asingle chip ball grid array (BGA) package or flip chip (FC) package tothe types of multi-chip package and module package, such as System inPackage (SiP), System Integrated Package (SIP) and System in Board(SiB).

These types of multi-chip package and module package are formed byattaching each semiconductor chip on the carrier board one by one usingthe flip-chip, the wire-bonding, or the SMT techniques. Although thesetechniques can admit high number of leads, when they perform under highfrequency or high speed, the conductive paths may be too long, whichlimit the electrical efficiency. In addition, since multiple interfacesare required in these conventional techniques, the production cost isincreased corresponsively.

Accordingly, to efficiently increase the electrical quality for theelectronic devices of the next generation, a method of embeddingsemiconductor chip in a carrier board to achieve direct electricalconnection is often adopted in the industry, so as to reduce theelectrical transmission path, thereby reducing the loss of electricalsignals and the distortion of the same, and improving the capability ofhigh speed operation.

As shown in FIG. 1, a cross-sectional view of a conventional packagewith semiconductor chips embedded therein is shown. As shown in thedrawing, the package comprises: a carrier board 10, which has at leastone opening 100 a formed on one surface 100 thereof; at least onesemiconductor chip 11 having an inactive surface 11 b and an opposingactive surface 11 a, on which a plurality of electrode pads 110 areformed, and therewith the semiconductor chip 11 received in the opening100 a of the carrier board 10; a built-up structure 12 formed on thecarrier board 10, which is electrically connected to the electrode pads110 of the semiconductor chip 11 through a plurality of conductive vias120. The inactive surface 11 b of the semiconductor chip 11 is attachedinto the opening 100 a of the carrier board 10 via an adhesive 13.

The built-up structure 12 comprises at least one insulating layer 121,at least one circuit layer 122 stacked on the insulating layer 121 and aplurality of conductive vias 120 in the insulating layer 121 toelectrically connect the circuit layer 122. The outermost surface of thebuilt-up structure 12 has a plurality of electrical connecting pads 123and the outermost built-up structure is covered with a solder mask layer124. The solder mask layer 124 has a plurality of openings for exposingthe electrical connecting pads 123, which can be mounted with the solderballs 125.

However, in order to save production cost, a plurality of semiconductorchips are often embedded in a carrier board. Then after a circuitmanufacturing completed to form a circuit to thereby extend electricalconnections for the semiconductor chip, a cutting process on the carrierboard is performed to carry out individual package with a semiconductorchip embedded therein. Nevertheless, in the foregoing method, a spacemust be preserved in the layout design on the carrier board for thesubsequent cutting process using the shaping machine, as a router. Sincethe shaping machine is relatively large, the preserved space of thecarrier board must also be large, thus reducing the usable layout spaceof the carrier board, and increasing the production cost.

Furthermore, after the semiconductor chip has been embedded in thecarrier board following the foregoing method, a process of circuitpatterning is carried out on only one surface of the substrate. Thismakes the two opposing surfaces of the package suffer from unbalancedstresses, thereby causing warpage of the carrier board during theprocess, as well as reducing product yield.

Moreover, in the conventional process, the shaping machine performscutting on the carrier board directly, thus the shaping time can notdecrease. In addition, as the circuit is made of copper which is highlyextensible upon stress exerted by the shaping machine, it may causescratch of the adjacent semiconductor packages after the cuttingprocess, resulting in damages in the package and reduction in theproduct yield.

Thus, there is an urgent need for the industry to develop a structurewith semiconductor chips embedded therein and a method of fabricatingthe same, in which the problems such as reduction in usable space of thecarrier board, inefficient layout design, substrate warpage, damages insemiconductor package, low product yield, increased cost, and increasedtime for shaping can be solved.

SUMMARY OF THE INVENTION

In light of the drawbacks of the prior arts described above, a primaryobjective of the present invention is to provide a structure withsemiconductor chips embedded therein and a fabricating method thereof,for efficient layout of the chip carrier board and increasing usablespace of the carrier board.

Another objective of the invention is to provide a structure withsemiconductor chips embedded therein and a fabricating method thereof,to thereby balance out the stresses exerted on the carrier board duringthe fabricating process, thus preventing the occurrence of warpage whichdamages the overall package structure.

Further objective of the invention is to provide a structure withsemiconductor chips embedded therein and a fabricating method thereof,for increasing yield, reducing the cost and shaping time.

To achieve the foregoing and other objectives, the present inventionproposes a method of fabricating a structure with semiconductor chipsembedded therein, comprising: providing a carrier board having a firstsurface and an opposing second surface, therewith forming both aplurality of through openings in the carrier board, and first trencheson the first surface thereof surrounding the through openings withoutpenetrating the carrier board; providing a first dielectric layer, andputting the first surface of the carrier board on the first dielectriclayer; disposing a semiconductor chip within each of the throughopenings of the carrier board, wherein the semiconductor chip has anactive surface and an opposing inactive surface, which likewise is puton the first dielectric layer, and then pressing to bond together thecarrier board, the semiconductor chip, and the first dielectric layer,so that the first dielectric layer fills the first trenches, as well asthe gap between the semiconductor chip and the carrier board; andforming second trenches on the second surface of the carrier board atthe positions corresponding to the first trenches, therebyinterconnecting mutually to form through trenches in the carrier board.

The foregoing method further comprises: forming a second dielectriclayer both on the second surface of the carrier board and on the activesurface of the semiconductor chip, so that the second dielectric layerfills the second trenches; and forming a plurality of conductive vias inthe second dielectric layer, as well as forming a circuit layer on thesecond dielectric layer, wherein the conductive vias electricallyconnect to the active surface of the semiconductor chip. Moreover, themethod also comprises: forming a metal layer on the outer surface of thefirst dielectric layer at the same time as forming the circuit layer onthe second dielectric layer.

In addition, forming a built-up structure on the second dielectric layerand on the circuit layer, which electrically connects with the circuitlayer, wherein at the same time as forming the built-up circuit layer,another metal layer is successively stacked on the metal layer so as toform a metallic board with a multi-layer structure.

Furthermore, the method comprises forming a solder mask layer on thebuilt-up structure, wherein the solder mask layer has a plurality ofopenings, to thereby expose the connecting pads of the built-upstructure, and forming openings in the metallic board at the positionscorresponding to the through trenches. After a cutting process via thethrough trenches, a plurality of packages are formed, each having astructure with the semiconductor chip embedded and the circuit layerintegrated therein, wherein some residual of the first dielectric layeris present around the periphery of the package.

The present invention also proposes a structure with semiconductor chipsembedded therein, comprising: a carrier board having a first surface andan opposing second surface, therewith a plurality of through openingsformed in the carrier board, and through trenches surrounding thethrough openings formed in the same; a plurality of semiconductor chips,which have an active surface and an opposing inactive surface each,received in the through openings of the carrier board; and a firstdielectric layer formed on the first surface of the carrier board,filling the gap between the semiconductor chip and the carrier board, aswell as parts of the through trenches.

The foregoing structure further comprises: a second dielectric layerformed on the second surface of the carrier board and on the activesurface of the semiconductor chip, also filling the residual spaces ofthe through trenches; and a circuit layer formed on the seconddielectric layer, together with a plurality of conductive vias formed inthe second dielectric layer, to thereby electrically connect to theactive surface of the semiconductor chip.

Subsequently, a built-up structure can be formed on the seconddielectric layer and the circuit layer. The built-up structure iselectrically connected to the circuit layer.

Besides, the structure of the invention comprises a metallic boardformed on the outer surface of the first dielectric layer, and openingsare formed in the metallic board at the positions corresponding to thethrough trenches, which are then used for a cutting process to therebyform a plurality of packages, each having a structure with thesemiconductor chip embedded and the circuit layer integrated therein,wherein some residual of the first dielectric layer is present aroundthe periphery of the package.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully comprehended by reading thedetailed description of the preferred embodiment listed below, withreference to the accompanying drawings, wherein:

FIG. 1 (PRIOR ART) is a schematic cross-sectional diagram showing aconventional package with a semiconductor chip embedded therein; and

FIGS. 2A-2I are schematic cross-sectional diagrams showing the method inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described indetail below while referring to FIGS. 2A-2I.

As shown in FIG. 2A, firstly a carrier board 20 is provided. The carrierboard 20 has a first surface 20 a and an opposing second surface 20 b,therewith forming a plurality of through openings 200 therein, togetherwith first trenches 201 on the first surface 20 a thereof surroundingthe through openings 200 without penetrating the carrier board 20. Theforegoing carrier board 20 can be a heat sink made of metal or aninsulating board made of BT resin, RF4 resin, epoxy resin, glass fibre,polyimide, cyanate ester or a circuit board having circuit structure. Inthe present invention, the first trenches 201 are formed by etching orrouting.

As shown in FIGS. 2B and 2C, a first dielectric layer 210 is provided,and then the first surface 20 a of the carrier board 20 is put on thefirst dielectric layer 210; a semiconductor chip 22 is disposed withineach of the through openings 200 of the carrier board 20, wherein thesemiconductor chip 22 has an active surface 220 and an opposing inactivesurface 221, which likewise is put on the first dielectric layer 210. Aremovable protective film (not shown in the figures) is attached ontoboth the second surface 20 b of the carrier board 20 and the activesurface 220 of the semiconductor chip 22, and then press to bondtogether the carrier board 20, the semiconductor chip 22, and the firstdielectric layer 210, so that the first dielectric layer 210 fills thefirst trenches 201, as well as the gap between the semiconductor chip 22and the carrier board 20, therewith the semiconductor chip 22 fixed inposition within the through opening 200 of the carrier board 20 via thefirst dielectric layer 210.

The first dielectric layer 210 can be made of epoxy resin, polyimide,cyanate ester, ajinomo build-up film, bismaeleimide triazine (BT) or amixed epoxy resin and FR5 glass fiber; and the first dielectric layer210 can further comprise a metal film 211 formed on one surface thereof,which is not in contact with the carrier board 20. The metal film 211 ispreferably made of copper (Cu) which has high conductivity and can bepressed or deposited on the first dielectric layer in advance. Toprovide a good adhesion for a subsequent electro-plating to form metallayers, it is preferred to apply a surface roughness treatment on thesurface of the first dielectric layer 210 before the formation of themetal film 211.

A plurality of electrode pads 2200 are formed on the active surface 220of the semiconductor chip 22.

As shown in FIG. 2D, a plurality of second trenches 202 are formed onthe second surface 20 b of the carrier board 20 at the positionscorresponding to the first trenches 201, to thereby interconnectmutually to form through trenches 203 in the carrier board 20 for asubsequent cutting process using the shaping machine, such as a router.Accordingly, the space of the carrier board can be more efficientlyused, improving the efficiency of circuit layout. Moreover the throughtrenches 203 with the use of shaping machine allows simple cuttingprocess to be achieved to carry out a single semiconductor package witha semiconductor chip 22 embedded therein, thereby reducing the shapingtime and the cost.

As shown in FIG. 2E, a second dielectric layer 23 is pressed onto thesecond surface 20 b of the carrier board 20 and on the active surface220 of the semiconductor chip 22, and fills the second trenches 202. Aplurality of openings 230 are formed in the second dielectric layer 23to expose the electrode pads 2200 of the semiconductor chip 22. Aplurality of conductive vias 240 are formed in the second dielectriclayer 23, as well as a circuit layer 24 is formed on the same, whereinthe conductive vias 240 electrically connect to the electrode pads 2200.

In addition, at the same time as forming the circuit layer 24, it isalso applicable to form a metal layer 212 (such as a copper layer) onthe metal film 211 on the outer surface of the first dielectric layer210 through a plating process.

As shown in FIG. 2F, a build-up process can be performed selectivelyaccording to the practical needs, to form a built-up structure 25 on thesecond dielectric layer 23 and on the circuit layer 24, comprising: atleast a dielectric layer 250, at least a built-up circuit layer 251 astacked on the dielectric layer 250, a plurality of connecting pads 251b, and a plurality of conductive vias 251 c, to thereby electricallyconnect to the circuit layer 24.

Besides, at the same time as forming the built-up circuit layer 251 a,it is also applicable to stack another metal layer successively on themetal layer 212 through plating process, so as to form a metallic board213 with a multi-layer structure. The metallic board 213 is used as aheat sink for dissipating heat generated from the semiconductor chip 22,and furthermore, the metallic board 213 as well as the first dielectriclayer 210 serves to balance out the stresses exerted on the carrierboard during the build-up process, thereby preventing the occurrence ofwarpage which damages the overall package structure, thus increasing theproduct yield and reducing the cost.

As shown in FIG. 2G, a solder mask layer 26 can be formed on the outersurface of the built-up structure 25, wherein the solder mask layer 26has a plurality of openings 260, to thereby expose the connecting pads251 b of the outermost circuit in the built-up structure 25. Moreover,conductive elements can then be attached to the connecting pads 251 b,thereby extending the electrical connection of the semiconductor chiptowards outside of the package.

As shown in FIG. 2H, openings 27 are formed in the metallic board 124 atthe positions corresponding to the through trenches 203 for a subsequentcutting process. FIG. 2I shows one of a plurality of packages carriedout through the cutting process, with the semiconductor chip 22 embeddedand the circuit layers 24, 251 a integrated therein, wherein someresidual of the first dielectric layer 210 is present around theperiphery of the package.

The present invention also proposes a structure with semiconductor chipsembedded therein, as shown in FIG. 2H, comprising: a carrier board 20having a first surface 20 a and an opposing second surface 20 b,therewith a plurality of through openings 200 formed in the carrierboard 20, together with through trenches 203 formed in the samesurrounding the through openings 200; a plurality of semiconductor chips22, which have an active surface 220 and an opposing inactive surface221 each, received in the through openings 200 of the carrier board 20;and a first dielectric layer 210 formed both on the first surface 20 aof the carrier board 20 and on the inactive surface 221 of thesemiconductor chips 22 each, filling the gaps between the semiconductorchips 22 and the carrier board 20, as well as parts of the throughtrenches 203.

The foregoing structure further comprises: a second dielectric layer 23formed both on the second surface 20 b of the carrier board 20 and onthe active surface 220 of the semiconductor chips 22 each, also fillingthe residual spaces of the through trenches 203; and a circuit layer 24formed on the second dielectric layer 23, together with a plurality ofconductive vias 240 formed in the same, to thereby electrically connectto the active surface 220 of the semiconductor chip 22.

Subsequently, a built-up structure 25 can be formed on the seconddielectric layer 23 and the circuit layer 24. The built-up structure 25is electrically connected to the circuit layer 24.

Besides, the structure of the invention comprises a multi-layer metallicboard 213 formed on the outer surface of the first dielectric layer 210,and openings 27 are formed in the metallic board 213 at the positionscorresponding to the through trenches 203, which are then used for acutting process to thereby form a plurality of packages, each having astructure with the semiconductor chip 22 embedded and the circuit layer24, 251 integrated therein, wherein some residual of the firstdielectric layer 210 is present around the periphery of the package, asshown in FIG. 2I.

In comparison with the conventional technology, the structure and themethod of the present invention provides through trenches for cutting,to thereby effectively enhance the usable space of the carrier board.

In addition, after the carrier board is made up, the first and seconddielectric material together fix the semiconductor chips in positionwithin the carrier board, followed by forming the circuit layers on oneside, along with a metallic board on the other side as a heat sink.Furthermore, the metallic board as well as the first dielectric layerserves to balance out the stresses exerted on the carrier board duringthe build-up process, to thereby reduce the occurrence of warpage, aswell as increasing the product yield and reducing the cost.

Moreover, the through trenches in the carrier board provided for thesubsequent cutting process also prevents reciprocal scratching anddamage in adjacent semiconductor packages due to the extension of thecircuit made of copper which is highly extensible upon stress exerted bythe shaping machine.

While the preferred forms of the present invention have been described,it is to be understood that modifications will be apparent to thoseskill in the art without departing from the spirit of the invention. Thescope of the invention, therefore, is to be determined solely by thefollowing claims.

1. A method of fabricating a structure with semiconductor chips embeddedtherein, comprising: providing a carrier board having a first surfaceand an opposing second surface, therewith forming a plurality of boththrough openings in the carrier board, and first trenches on the firstsurface thereof surrounding the through openings without penetrating thecarrier board; providing a first dielectric layer, and putting the firstsurface of the carrier board on the first dielectric layer; providing asemiconductor chip, which has an active surface and an opposing inactivesurface, therewith disposing the semiconductor chip within each of thethrough openings of the carrier board, whose inactive surface likewiseis on the dielectric layer, and then pressing to bond together thecarrier board, the semiconductor chip, and the first dielectric layer,so that the first dielectric layer fills the first trenches and the gapbetween the semiconductor chip and the carrier board; and forming secondtrenches on the second surface of the carrier board at the positionscorresponding to the first trenches, thereby interconnecting mutually toform through trenches in the carrier board.
 2. The method of claim 1,wherein the first dielectric layer further comprises a metal film formedon one surface thereof, which is not in contact with the carrier board.3. The method of claim 1, further comprising: forming a seconddielectric layer on the second surface of the carrier board and on theactive surface of the semiconductor chip, so that the second dielectriclayer fills the second trenches; and forming a plurality of conductivevias in the second dielectric layer, as well as forming a circuit layeron the second dielectric layer, wherein the conductive vias electricallyconnect to the active surface of the semiconductor chip.
 4. The methodof claim 3, further comprising forming a built-up structure on thesecond dielectric layer and on the circuit layer, wherein the built-upstructure includes: at least a dielectric layer, at least a built-upcircuit layer, a plurality of connecting pads, and a plurality ofconductive vias, to thereby electrically connect to the circuit layer onthe second dielectric layer.
 5. The method of claim 3, wherein at thesame time as forming the circuit layer on the second dielectric layer, ametal layer is formed on the outer surface of the first dielectriclayer.
 6. The method of claim 4, wherein at the same time as forming thebuilt-up circuit layer, a metal layer is successively stacked on theouter surface of the first dielectric layer so as to form a metallicboard with a multi-layer structure.
 7. The method of claim 6, furthercomprising forming openings in the metallic board at the positionscorresponding to the through trenches.
 8. The method of claim 7, furthercomprising using the through trenches in the carrier board for a cuttingprocess to form a package structure with the semiconductor chip embeddedand the circuit layer integrated therein, wherein some residual of thefirst dielectric layer is present around the periphery of the package.9. The method of claim 1, wherein the carrier board is one of a heatsink made of metal, an insulating board, and a circuit board.
 10. Astructure with semiconductor chips embedded therein, comprising: acarrier board having a first surface and an opposing second surface,therewith a plurality of through openings formed in the carrier board,and through trenches surrounding the through openings formed in thesame; a plurality of semiconductor chips having an active surface and anopposing inactive surface each, received in the through openings of thecarrier board; and a first dielectric layer formed on the first surfaceof the carrier board, and filling the gap between the semiconductor chipand the carrier and parts of the through trenches.
 11. The structure ofclaim 10, further comprising: a second dielectric layer formed on thesecond surface of the carrier board and on the active surface of thesemiconductor chip, also filling the residual spaces of the throughtrenches; and a circuit layer formed on the second dielectric layer,together with a plurality of conductive vias formed in the same, tothereby electrically connect to the active surface of the semiconductorchip.
 12. The structure of claim 11, further comprising a built-upstructure on the second dielectric layer and on the circuit layer,wherein the built-up structure includes: at least a dielectric layer, atleast a built-up circuit layer, a plurality of connecting pads, and aplurality of conductive vias, to thereby electrically connect to thecircuit layer on the second dielectric layer.
 13. The structure of claim10, further comprising a metallic board formed on the outer surface ofthe first dielectric layer.
 14. The structure of claim 13, furthercomprising openings formed in the metallic board at the positionscorresponding to the through trenches.
 15. The structure of claim 10,wherein the carrier board is one of a heat sink made of metal, aninsulating board, and a circuit board.
 16. A structure with asemiconductor chip embedded therein, comprising: a carrier board havinga first surface and an opposing second surface, therewith a throughopening formed in the carrier board; a semiconductor chip having anactive surface and an opposing inactive surface, received in the throughopening of the carrier board; a first dielectric layer formed on thefirst surface of the carrier board, and some residual of the firstdielectric layer is present around the periphery of the carrier board;and a second dielectric layer formed on the second surface of thecarrier board and on the active surface of the semiconductor chip. 17.The structure of claim 16, further comprising a circuit layer formed onthe second dielectric layer, together with a plurality of conductivevias formed in the same, to thereby electrically connect to the activesurface of the semiconductor chip.
 18. The structure of claim 17,further comprising a built-up structure on the second dielectric layerand on the circuit layer, wherein the built-up structure includes: atleast a dielectric layer, at least a built-up circuit layer, a pluralityof connecting pads, and a plurality of conductive vias, to therebyelectrically connect to the circuit layer on the second dielectriclayer.
 19. The structure of claim 16, further comprising a metallicboard formed on the outer surface of the first dielectric layer.
 20. Thestructure of claim 16, wherein the carrier board is one of a heat sinkmade of metal, an insulating board, and a circuit board.